
module Control_unit(
    input [31:0] idata,
    output reg [3:0] we,
    output reg [31:0] imm,
    output reg wer
);

    always @(*) begin
        case (idata[6:0])
            7'b0110011: begin
                wer = 1; we = 4'b0000;
            end
            7'b0010011: begin
	            wer = 1; we = 4'b0000; imm = {{20{idata[31]}}, idata[31:20]};
            end
            7'b0000011: begin   //L
                wer = 1; we = 4'b0000; imm = {{20{idata[31]}}, idata[31:20]};
            end
            7'b0100011: begin   //S type
	            imm = {{20{idata[31]}},idata[31:25],idata[11:7]};
	            wer=0;
	            case (idata[14:12])
                    3'b000: we = 4'b0001;
                    3'b001: we = 4'b0011;
                    3'b010: we = 4'b1111;
                    default: we = 4'b0000;
               endcase
            end
            7'b1100011: begin   //Btype
                wer = 0; we = 4'b0000; imm = {{20{idata[31]}}, idata[31], idata[7], idata[30:25], idata[11:8], 1'b0};
            end
            7'b1100111:begin    //
	            wer = 1;we = 4'b0;imm = {{20{idata[31]}},idata[31:20]};
            end
            7'b1101111:	begin
	            wer = 1;we = 4'b0;imm = {{11{idata[31]}},idata[31],idata[19:12],idata[20],idata[30:21],1'b0};
            end
            7'b0010111:begin
	            wer = 1;we = 4'b0;imm = {idata[31:12],12'b0};
            end
            7'b0110111:begin
	            wer=1;we=4'b0;imm = {idata[31:12],12'b0};
            end
            default: begin
                wer = 0; we = 4'b0000; imm = 32'b0;
            end
        endcase
        
    end
endmodule

